Open Source Inspired Hardware (and their happy friends)

Briefly introduce the structure of Spike, how it simulates the RISC-V instruction. Briefly introduce how SystemC works, and some types of SystemC models, and the open source SystemC model we use : VCML ( Virtual Components Modeling Library ). Introducing how Spike-VP works, and doing some experiments with Spike-VP, like run the linux kernel, and run a small benchmark program.

講者

Tommy

菜鳥工程師

你是否想過打造自己的 CPU 並用來執行多種應用程式？拜開放原始碼軟硬體技術所賜，RISC-V 和 Linux 強強聯手，可讓我們用低廉的成本達到這目標。本議程介紹在 PYNQ-Z2 開發板實作 RISC-V 處理器，並逐步開發配合的硬體周邊，在 FPGA 驗證後，陸續以 OpenSBI 和 Linux 核心的移植進行更深入的整合驗證，引導會眾體驗開放原始碼軟硬體背後的奧秘。

講者

林志懋

成大電機應屆畢業生，期許自己能在現今複雜處理器設計中找到可貢獻之處。

The advancement of open science hardware is transforming the landscapes of education and research, democratizing access to scientific inquiry and discovery. In this presentation, I will explore the significant role of ExpEYES, a Python-powered open-source pocket science lab, in this revolution. Utilizing ExpEYES within diverse educational settings has enabled students to engage directly with complex scientific concepts through hands-on experiments. Moreover, my work extends beyond the classroom into the realm of research, where I have employed ExpEYES to develop innovative open science hardware solutions such as cyclic voltammetry setups, PE loop tracers, and devices to analyze motion and oscillations. This talk will detail these applications, showcasing how ExpEYES serves as a bridge between learning and real-world scientific investigation, and illustrating the potential of open hardware to foster a more inclusive and collaborative scientific community.

講者

Praveen Patil

A physics teacher, Python enthusiast, and advocate for open-source software and hardware. He actively volunteers to promote ExpEYES and SEELab, a Python-powered pocket science lab that brings real-time scientific experimentation to students and researchers.

Google Summer of Code alumnus for three years with FOSSASIA (2014, 2015, and 2016). Praveen has mentored young programmers through the Google Code-In program and volunteered with Fedora.

He is the founder of Makerspace Belgaum and the organizer of Science Hack Day India. Praveen was also part of the ICT curriculum design team and contributed to the National Repository of Open Educational Resources (NROER) at CIET, NCERT in New Delhi.

In his work, he focuses on creating resources that help students visually grasp complex scientific and mathematical principles using Python programming. He is continuously experimenting and exploring ways to use Python, ExpEYES, and SEELab to actively engage students and enhance their understanding of scientific and mathematical concepts. He is currently pursuing PhD in Physics.

Links: Personal Website: https://www.gnovi.in/ ExpEYES: https://expeyes.in/ SEELab: https://csparkresearch.in/seelab3 Github: https://github.com/wavicles

The presenters are members of the "CPU-dev" group, a technical community dedicated to hobby CPU design. They recently participated in MPW-3, successfully completing the tape-out of their own 8-bit ISA CPU design. While they had prior experience designing soft CPUs using FPGAs, this marked their inaugural attempt at silicon tape-out. Today, they will share their journey of developing the CPU using open-source EDA tools.

講者

Yuki Azuma

Yuki Azuma is a first-year master’s student at the University of Tsukuba, specializing in physics. His hobby lies in creating things such as CPUs and operating systems to understand their mechanisms. During his fourth year at a technical college, together with his friend Kazuhide, he embarked on designing an 8-bit ISA CPU. Using open-source tools, they ultimately succeeded in fabricating a genuine LSI.

講者

Kazuhide Uchiyama

Kazuhide Uchiyama is a first-year master's student at the National Institute of Informatics, specializing in computer architecture. Since his undergraduate years, he has been familiar with FPGA and computer architecture, and in his third year of university, he successfully taped out a CPU using only open-source software. He writes articles in both Japanese and English on his personal website, vlsi.jp. Twitter:@Cra2yPierr0t

The topic of this talk is the ongoing development of the IHP SG13G2 open-source Process Design Kit (PDK), a crucial resource for advancing analog, pure digital, mixed-signal, and RF design. We will explore the toolset provided within the PDK, including layout, simulation, and verification tools, like KLayout and ngspice. The discussion will also cover the collaborative efforts in refining device models and DRC rules, aiming to bridge the gap between innovative semiconductor research and practical, manufacturable designs. Attendees will gain insights into the challenges and solutions in PDK and EDA tool development, underscoring the importance of community contributions and open-source collaboration.

講者

Frank Vater

None

For the past few years, open source hardware has gained momentum and open source hardware IPs, mainly based on RTL descriptions have found widespread use not only in academia, but in industry as well. With the advent of openly available process design kits (PDKs), and improved productivity of open source EDA tools, it is now possible to design not only simple designs, but much complex systems-on-chip (SoCs) using an end-to-end open design flow as well as publish the physical design and implementation scripts. In this session, you will learn how to design a digital chip step by step using only open-source software. You will be guided through the entire process of designing a small microcontroller on your own PC. We also present our larger Linux-capable SoC, outlining design challenges at this scale and how we solved them. Finally, we discuss which additional improvements will be needed for open-source EDA tools to tackle even larger designs.

講者

Philippe Sauter

None

There is still very few free/open-source/multiple issue/in-order/softcore CPU in the wild. At the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !

VexiiRiscv aim at : - Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like) - Covering both 32 bits and 64 bits RISC-V + IMAFDC + B - Being very modular and extendable - Being Debian capable - Being FPGA friendly

This talk should normaly run on the hardware itself (FPGA + VexiiRiscv + Debian), minus maybe, some kernel panics ^.^

講者

Dolu1990

Working in open-source hardware since 2015. Here is a few projects : - Hardware description library : SpinalHDL - RISC-V CPU : VexRiscv, VexiiRiscv, NaxRiscv

I'm working as an independent, living from the project listed above.

Can you design a commercial chip, shipping hundred of millions of it? The OpenHW Group is dedicated to curate and maintain with it's members industrial quality, open source RISC-V IP with full verification and documentation under a permissive license. OpenHW Group RISC-V IP has been already shipped in many different commercial applications and is best suited for custom extensions or modification if you wish but also works off-the-shelf. Let us give an overview about our Core line up and how we enable embedded IoT, edge AI and a variety of other applications.

講者

Florian 'Flo' Wohlrab

Flo is the CEO of the OpenHW Group and international not-for-Profit organization dedicated to curate and maintain high quality, industrial grade, open source RISC-V Cores. Flo is fascinated by RISC-V and help to smoothen accessibility to high quality RISC-V and help promote the RISC-V ISA worldwide. He is also one of the first RISC-V International Ambassadors. Before leading the OpenHW Group Flo was Head of Sales for a commercial RISC-V provider where he took care of the markets in Japan, Europe and Middle East.