VexiiRiscv : Pushing FPGA softcore performances forward By Dolu1990

議題

VexiiRiscv : Pushing FPGA softcore performances forward

TR611 [[ new Date( '2024-08-04 06:30:00+00:00' ).toLocaleDateString('ja', {year: 'numeric', month: '2-digit', day: '2-digit'}) ]] [[ new Date( '2024-08-04 06:30:00+00:00' ).toLocaleTimeString('zh-Hant', {hour12: false, hour: '2-digit', minute:'2-digit'}) ]] ~ [[ new Date( '2024-08-04 07:00:00+00:00' ).toLocaleTimeString('zh-Hant', {hour12: false, hour: '2-digit', minute:'2-digit'}) ]] 英文 English

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There is still very few free/open-source/multiple issue/in-order/softcore CPU in the wild. At the same time, VexRiscv accumulated quite some technical debt and limitations. So it was time to fill those gaps !

VexiiRiscv aim at : - Providing a free/open-source CPU which can scale from simple micro controller, up to linux ready multi-core / multi-issue cluster (Cortex A53/A55 like) - Covering both 32 bits and 64 bits RISC-V + IMAFDC + B - Being very modular and extendable - Being Debian capable - Being FPGA friendly

This talk should normaly run on the hardware itself (FPGA + VexiiRiscv + Debian), minus maybe, some kernel panics ^.^

講者

Dolu1990

Working in open-source hardware since 2015. Here is a few projects : - Hardware description library : SpinalHDL - RISC-V CPU : VexRiscv, VexiiRiscv, NaxRiscv

I'm working as an independent, living from the project listed above.

Open Source Inspired Hardware (and their happy friends) PVAHAS general (30mins)