篩選條件
議題
Vortex is an open source Hardware and Software project to support GPGPU based on RISC-V ISA extensions. Currently Vortex supports OpenCL/CUDA and it runs on FPGA. The vortex platform is highly customizable and scalable with a complete open source compiler, driver and runtime software stack to enable research in GPU architectures/compiler/run-time systems.
講者
Blaise Tine
Blaise Tine is a Professor in Computer Science Department at University of California, Los Angeles. He is a recent PhD Student graduate in the school of Computer Science at Georgia Institute of Technology, where he has lead the Vortex project. His research interests are in the area of hardware accelerators and software co-design, focusing in the architecture design, programming languages and compiler tools to support heterogenous computing. He is also interested in domain-specific applications of accelerators such as 3D graphics, graphs analytics, and machine learning.
CUDA is the dominant language for parallel programming on GPU architecture, though other GPU programming languages, such as OpenCL and OpenMP exist. However, its use has been largely limited to NVIDIA devices, leading to recent efforts to enable its use on other platforms, such as CPUs and AMD/Intel GPUs. We aim to extend the reach of CUDA to RISC-V systems.
講者
Hyesoon Kim
Hyesoon Kim is professor in the School of Computer Science at the Georgia Institute of Technology and a co-director of center for novel computing hierarchy. Her research areas include the intersection of computer architectures and compilers, with an emphasis on heterogeneous architectures, such as GPUs and near-data-processing. She is a recipient of NSF Career award and is a member of Micro Hall of Fame. She is the chair of IEEE TCuARCH. Her research has been recognized with a best paper award at PACT 2015. She is an associate editor of Transactions on Architecture and Code Optimization and IEEE-CAL.
Main focus of this talk is the SG13G2 Open Source PDK for IHP 130nm BiCMOS technology. One year ago, it was announced that IHP will publish an open source PDK for its SG13G2 technology. Since this is a long-term project, the current state will be presented. This includes the experiences and a road map for future work. The already known challenges and open issues will be addressed. Finally, an overview about multi-project wafer offer of IHP will be given.
講者
Frank Vater
Frank Vater studied information and media technology at Technical University of Cottbus (Germany) and recieved his master degree in 2007. He joined as scientist in IHP with main focus on hardware development for microcontroller and cryptographic cores. In 2017 he got his PhD in area of secure scan-chain test of ASICs. Finally he joined the position of project leader for PDK development in IHP in 2018.
Development of open source silicon platforms applicable to difficult real world use cases, much as Linux has become in the operating system space, quickly run into difficulty. A CPU ISA or small system on chip is only one part of a platform. The diverse and complex interfaces, signal processing, and compute tasks such a platform is called upon to provide mean a system approach is necessary.
We outline our experience building the J-Core platform, and how scratching our own itches lead to counter intuitive design decisions. Designed from the ground up to cover mixed signal processing in systems with complex and secure edge computing tasks, we also needed portability to multiple FPGA families, low cost silicon processes, and scalability for performance on advanced process nodes.
J-core is a completely open source platform, from the transistors through the OS and end user applications. Designed in the context of real world product development and deployments, the resulting platform is unique in the open hardware space.
講者
D. Jeff Dionne
Jeff is the original author of the uClinux kernel and OS. He has been designing and building open embedded systems with linux since the 1990s.
An overview of Google's investment in Taiwan and the open source community.
講者
Jason Ma, Ph.D.
As the Engineering Director, Jason Ma oversees Google Taiwan’s site growth, business management and development, as well as leads multiple R&D projects across the board. Before taking this leadership role at Google Taiwan, Jason was a Platform Technology and Cloud Computing expert in the Platform & Ecosystem business group at Google Mountain View, CA. In his 12 years with Google, Jason has successfully led strategic partnerships with global hardware and software manufacturers and major chip providers to drive various innovations in cloud technology. These efforts have not only contributed to a substantial increase in Chromebook’s share in global education, consumer and enterprise markets, but have also attracted global talents to join Google and its partners in furthering the
development of hardware and software technology solutions/services. Prior to joining Google, Jason served on the Office group at Microsoft Redmond, WA. He represented the company in a project, involving Merck, Dell, Boeing, and the United States Department of Defense, to achieve solutions in unified communications and integrated voice technology. In 2007, Jason was appointed Director of the Microsoft Technology Center in Taiwan. During which time, Jason led the Microsoft Taiwan technology team and worked with Intel and HP to establish a Solution Center in Taiwan to promote Microsoft public cloud, data center, and private cloud technologies, connecting Taiwan’s cloud computing industry with the global market and supply chain. Before joining Microsoft, Jason was Vice President and Chief Technology Officer at Soma.com. At Soma.com, Jason led the team in designing and launching e-commerce services, and partnered with Merck and WebMD on health consultation services and over the counter/prescription drugs/services. Soma.com was in turn acquired by CVS, the second largest pharmacy chain in the United States, forming CVS.com, where Jason served as Vice President and Chief Technology Officer and provided solutions for digital integration. Jason graduated from the Department of Electrical Engineering at National Cheng Kung University, subsequent which he moved to the United States to further his graduate studies. In 1993, Jason obtained a Ph.D. in Electrical Engineering from the University of Washington, with a focus in the integration and innovation of power systems and AI Expert Systems. In 1997, Jason joined the National Sun Yat-sen University as an Associate Professor of Electrical Engineering. To date, Jason has published 22 research papers and co-authored 2 books. Due to his outstanding performance, Jason was nominated and listed in Who's Who in the World in 1998.
An overview and retrospective of Google's efforts to empower semiconductor research using open source PDKs, software tools, and shared manufacturing.
HackMD 共筆：https://hackmd.io/@coscup/ryuYiKQs3/edit
講者
Aaron Cunningham
Aaron is a technical program manager focused on hardware developer tools for chip design at Google. He also supports Google's Open Source Programs Office, specializing in open source hardware to advise Alphabet’s portfolio on business strategy and best practices to build sustainable ecosystems. Previously, he’s led “maker” innovation efforts across Google and was a drone test pilot for Wing, an Alphabet company.
We are Boledu Foundation. Our missions are (1) Target and Extend the Google Open Source Silicon program and (2) to Design hands-on lab materials for training, (3) Promote IC education. For the Caravel Harness, We have developed a Caravel FPGA validation platform. In addition, we also develop a software debugging framework which includes GDBWave, and a Riscv-Tracer to facilitate the verification process. The GDBWave parses the waveform after RTL simulation to manipulate GDB debugging with VexRiscv CPU. The Riscv-Tracer helps to translate waveform display to Riscv instructions representation. The Caravel FPGA validation system enables users quickly prototype their user project design on the Xilinx PYNQ board. In addition, the FPGA design and hardware bitstream can be developed using the Vitis tool free from Xilinx, Then be validated on Boledu online PYNQ board with Jupyter Python3 testbench.
講者
Jiin Lai
We are Boledu Foundation. Our missions are (1) Target and Extend the Google Open Source Silicon program and (2) to Design hands-on lab materials for training. (3) Promote IC education Boledu funder, Jiin Lai is the Chief Technology Officer of VIA Electronics. He has over 30 years of experience in the PC industry and the past 12 years in the storage space. Earlier in his career, he was a software engineer developing EDA tools. He later co-founded VIA Electronics. He led the engineering team that developed Intel and AMD compatible chipsets and x86 compatible processor. For the past decade, he developed SSD controllers and later shifted his focus to developing distributed computing storage systems. His responsibilities include product and architecture development with an eye toward future computing architecture needs. Has more than 50 US patents. Since 2020, he has taught "Applied Acceleration and Advanced Synthesis" courses at NTU, NTHU and NYCU. He also founded the Life Bridge Educational Foundation to promote technology education in schools.
我們打造了 RSA256 這個專案，展示一套開發硬體時的標準流程，依序開發 C model 、SystemC model、再到 verilog module，並開發 Verilator 驗證框架，使每個階段間都能夠交互驗證，加速硬體開發的平行化與正確性。
講者
yodalee
大學修了電路可是出社會之後都在軟體公司寫軟體，最近換公司碰到許久沒碰的硬體，只覺得硬體好難，跟大學一樣都靠同學罩我 QAQ
講者
林裕盛
TODO...
Starting in 1990, Sorbonne Université-CNRS/LIP6 developped Alliance, a complete VLSI CAD toolchain released under GPL. In this spirit, we are assembling an upgraded design flow for ASICs based on FOSS tools like GHDL & Yosys for logical synthesis and Coriolis for physical design. We will present the flow with a focus on the Cotiolis part and some of the designs we made. This should be an important milestone toward the creation of an open hardware community.
講者
Jean-Paul.Chaput@lip6.fr
Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software Engineering. He joined the LIP6 laboratory within Sorbonne Université or SU (formerly UPMC) in 2000. Currently he is a Research Engineer in the Analog and Mixed Signal Team at LIP6. His main focus is on physical level design software. He is a key contributor in developing and maintaining the Alliance/Coriolis VLSI CAD projects for CMOS technologies. In particular he contributed in developing the routers of both Alliance/Coriolis and the whole Coriolis toolchain infrastructure. He his now a key contributor in extending Alliance/Coriolis to support advanced nodes and to the Analog Mixed-Signal integration.
講者
Naohiko Shimizu
Doctorate Degree: March 1994, Doctor of Engineering, Sophia University, Japan
Education: April 1991 to March 1994 Doctor of Science and Engineering, Sophia University, Post Graduate School of Electrical and Electronics Engineering April 1983 to March 1985 Master of Science and Engineering, Sophia University, Graduate School of Electrical and Electronics Engineering April 1979 to March 1983 Bachelor of Science and Engineering, Sophia University, Electrical and Electronics Engineering
Work Experience and Position: April 1995 to Present Tokai University April 1985 - March 1995 Hitachi Ltd. Co. Enterprise Computer Division.
November 2003 to Present CEO of IP ARCH, Inc. USA January 2010 to Present CTO of Overtone Corp. Japan
Successful open-source software inspires many technologies. Young engineers or students will learn many things from existing REAL designs. Unlike open-source software, VLSI design tasks are usually covered by NDA from fabrication companies and EDA tool vendors. It will prevent students to learn from existing designs. We wanted to change the situation. For educational purposes, we are trying to establish open VLSI fabrication methodologies. The methods are based on scalable cell libraries and scalable layout rules. With our method, we have made VLSI chips with several fabrication processes which will not require NDA from the designing students. These chips use legacy technologies such as 2-micron, 1.2-micron, 600nm, 350nm, and 180nm. But we believe that adaptations to other finer technologies will not be difficult and the method will contribute to the students and startups to learn faster from existing designs and challenge their own new ideas on VLSI.
講者
Naohiko Shimizu
Doctorate Degree: March 1994, Doctor of Engineering, Sophia University, Japan
Education: April 1991 to March 1994 Doctor of Science and Engineering, Sophia University, Post Graduate School of Electrical and Electronics Engineering April 1983 to March 1985 Master of Science and Engineering, Sophia University, Graduate School of Electrical and Electronics Engineering April 1979 to March 1983 Bachelor of Science and Engineering, Sophia University, Electrical and Electronics Engineering
Work Experience and Position: April 1995 to Present Tokai University April 1985 - March 1995 Hitachi Ltd. Co. Enterprise Computer Division.
November 2003 to Present CEO of IP ARCH, Inc. USA January 2010 to Present CTO of Overtone Corp. Japan