Starting in 1990, Sorbonne Université-CNRS/LIP6 developped Alliance, a complete VLSI CAD toolchain released under GPL. In this spirit, we are assembling an upgraded design flow for ASICs based on FOSS tools like GHDL & Yosys for logical synthesis and Coriolis for physical design. We will present the flow with a focus on the Cotiolis part and some of the designs we made. This should be an important milestone toward the creation of an open hardware community.
Jean-Paul Chaput holds a Master Degree in MicroElectronics and Software Engineering. He joined the LIP6 laboratory within Sorbonne Université or SU (formerly UPMC) in 2000. Currently he is a Research Engineer in the Analog and Mixed Signal Team at LIP6. His main focus is on physical level design software. He is a key contributor in developing and maintaining the Alliance/Coriolis VLSI CAD projects for CMOS technologies. In particular he contributed in developing the routers of both Alliance/Coriolis and the whole Coriolis toolchain infrastructure. He his now a key contributor in extending Alliance/Coriolis to support advanced nodes and to the Analog Mixed-Signal integration.
Doctorate Degree: March 1994, Doctor of Engineering, Sophia University, Japan
Education: April 1991 to March 1994 Doctor of Science and Engineering, Sophia University, Post Graduate School of Electrical and Electronics Engineering April 1983 to March 1985 Master of Science and Engineering, Sophia University, Graduate School of Electrical and Electronics Engineering April 1979 to March 1983 Bachelor of Science and Engineering, Sophia University, Electrical and Electronics Engineering
Work Experience and Position: April 1995 to Present Tokai University April 1985 - March 1995 Hitachi Ltd. Co. Enterprise Computer Division.
November 2003 to Present CEO of IP ARCH, Inc. USA January 2010 to Present CTO of Overtone Corp. Japan