By Jiin Lai
We are Boledu Foundation. Our missions are (1) Target and Extend the Google Open Source Silicon program and (2) to Design hands-on lab materials for training, (3) Promote IC education. For the Caravel Harness, We have developed a Caravel FPGA validation platform. In addition, we also develop a software debugging framework which includes GDBWave, and a Riscv-Tracer to facilitate the verification process. The GDBWave parses the waveform after RTL simulation to manipulate GDB debugging with VexRiscv CPU. The Riscv-Tracer helps to translate waveform display to Riscv instructions representation. The Caravel FPGA validation system enables users quickly prototype their user project design on the Xilinx PYNQ board. In addition, the FPGA design and hardware bitstream can be developed using the Vitis tool free from Xilinx, Then be validated on Boledu online PYNQ board with Jupyter Python3 testbench.
We are Boledu Foundation. Our missions are (1) Target and Extend the Google Open Source Silicon program and (2) to Design hands-on lab materials for training. (3) Promote IC education Boledu funder, Jiin Lai is the Chief Technology Officer of VIA Electronics. He has over 30 years of experience in the PC industry and the past 12 years in the storage space. Earlier in his career, he was a software engineer developing EDA tools. He later co-founded VIA Electronics. He led the engineering team that developed Intel and AMD compatible chipsets and x86 compatible processor. For the past decade, he developed SSD controllers and later shifted his focus to developing distributed computing storage systems. His responsibilities include product and architecture development with an eye toward future computing architecture needs. Has more than 50 US patents. Since 2020, he has taught "Applied Acceleration and Advanced Synthesis" courses at NTU, NTHU and NYCU. He also founded the Life Bridge Educational Foundation to promote technology education in schools.